ST52F510 datasheet(104/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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Bit 7: SPIF Serial Peripheral data transfer flag.

(read only)

This bit is set by hardware when a transfer

has

been

completed.

interrupt

generated if SPIE=1 in the SPI_CR register.

It is cleared by a software sequence (an

access to the SPI_STATUS_CR register

followed by a read or write to the SPI_IN/

SPI_OUT registers).

0: Data transfer is in progress or has been

approved by a clearing sequence.

1: Data transfer between the device and an

external device has been completed.

Note: While the SPIF bit is set, all writes to the

SPI_OUT register are inhibited.

Bit 6: WCOL Write Collision status (read only).

This bit is set by hardware when a write to the

SPI_OUT register is done during a transmit

sequence. It is cleared by a software

sequence (see Figure 15.5).

0: No write collision occurred

1: A write collision has been detected

Bit 5: OR SPI overrun error (read only).

This bit is set by hardware when the byte

currently being received in the shift register is

ready to be transferred into the SPI_IN

Overrun Condition). It is cleared by a

software

sequence

(read

the

SPI_STATUS_CR register followed by a

read in SPI_IN or write of the SPI_OUT

0: No overrun error.

1: Overrun error detected.

Bit 4: MODF Mode Fault flag (read only).

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section

15.4.5 Master Mode Fault). An SPI interrupt

can be generated if SPIE=1 in the SPI_CR

sequence

(An

access

the

SPI_STATUS_CR register while MODF=1

followed by a write to the SPI_CR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Bit 3: Not used.

Bit 2: SOD SPI output disable

This bit is set and cleared by software. When

set, it disables the alternate function of the

SPI output (MOSI in master mode / MISO in

slave mode)

0: SPI output not disable

1: SPI output disable.

Bit 1: SSM SS mode selection

This bit is set and cleared by software. When

set, it disables the alternate function of the

SPI Slave Select pin and use the SSI bit

value instead of.

0: SS pin used by the SPI.

1: SS pin not used (I/O mode), SSI bit value

is used.

Bit 0: SSI SS internal mode

This bit is set and cleared by software. It

replaces pin SS of the SPI when bit SSM is

set to 1. SSI bit is active low slave select

signal when SSM is set to 1.

0 : Slave selected

1 : Slave not selected.

Remark: It is recommended to write the SPI_CR

working in master mode, vice versa when working

in slave mode.

15.5.2 SPI Input Register.

SPI Data Input Register (SPI_IN)

Input Register 5 (05h) Read only

Reset Value: 0000 0000 (00h)

bit 7-0: SPIDI7-SPIDI0 Received data.

The SPI_IN register is used to receive data on the

serial bus.

Note: During the last clock cycle the SPIF bit is set,

a copy of the data byte received in the shift register

is moved to a buffer. When the user reads the

serial peripheral data I/O register, the buffer is

actually being read.

SPIDI7

SPIDI6

SPIDI5

SPIDI4

SPIDI3

SPIDI2

SPIDI1

SPIDI0

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