ADE75 datasheet(113/148 Pages) AD

113 / 148 page

Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 113 of 148

Mode 2 (8-Bit Timer/Counter with Autoreload)

Mode 2 configures the timer register as an 8-bit counter (TL0)

with automatic reload as shown in Figure 71. Overflow from

TL0 not only sets TF0, but also reloads TL0 with the contents of

TH0, which is preset by software. The reload leaves TH0

unchanged.

CONTROL

TF0

TL0

(8 BITS)

INTERRUPT

RELOAD

TH0

(8 BITS)

P0.6/T0

GATE

TR0

IN T

C/T = 0

C/T = 1

FCORE

Figure 71. Timer/Counter 0, Mode 2

Mode 3 (Two 8-Bit Timer/Counters)

Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in

Mode 3 simply holds its count. The effect is the same as setting

TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two

separate counters. This configuration is shown in Figure 72.

TL0 uses the Timer 0 control bits C/T, Gate, TR0, INT0, and

TF0. TH0 is locked into a timer function (counting machine

cycles) and takes over the use of TR1 and TF1 from Timer 1.

Therefore, TH0 then controls the Timer 1 interrupt. Mode 3 is

provided for applications requiring an extra 8-bit timer or

counter.

When Timer 0 is in Mode 3, Timer 1 can be turned on and off

by switching it out of and into its own Mode 3, or it can still be

used by the serial interface as a baud rate generator. In fact, it

can be used in any application not requiring an interrupt from

Timer 1 itself.

CONTROL

CORE

CLK/12

TF0

TL0

(8 BITS)

INTERRUPT

P0.6/T0

GATE

TR0

TF1

TH0

(8 BITS)

INTERRUPT

FCORE/12

TR1

INT

C/T = 0

C/T = 1

FCORE

Figure 72. Timer/Counter 0, Mode 3

TIMER 2

Timer/Counter 2 Data Registers

Timer/Counter 2 also has two pairs of 8-bit data registers

associated with it: Timer 2 High byte SFR (TH2, 0xCD), Timer

2 Low byte SFR (TL2, 0xCC), Timer 2 Reload/capture High byte

SFR (RACP2H, 0xCB) and Timer 2 Reload/capture Low byte

SFR (RACP2L, 0xCA). These are used as both timer data

registers and as timer capture/reload registers – see Table 104 to

Table 107.

Timer/Counter 2 Operating Modes

The following sections describe the operating modes for

Timer/Counter 2. The operating modes are selected by bits in

the Timer/Counter 2 Control SFR (T2CON, 0xC8) as shown in

Table 99 and Table 108.

Table 108. T2CON Operating Modes

RCLK (or) TCLK

CAP2

TR2

Mode

16-Bit Autoreload

16-Bit Capture

Baud Rate

Off

16-Bit Autoreload Mode

Autoreload mode has two options that are selected by bit

EXEN2 in Timer/Counter 2 Control SFR (T2CON, 0xC8). If

EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2 but

also causes the Timer 2 registers to be reloaded with the 16-bit

value in registers Timer 2 Reload/capture High byte SFR

(RACP2H, 0xCB) and Timer 2 Reload/capture Low byte SFR

(RACP2L, 0xCA), which are preset by software. If EXEN2 = 1,

Timer 2 still performs the above, but with the added feature that

a 1-to-0 transition at external input T2EX also triggers the 16-

bit reload and sets EXF2. Autoreload mode is shown in Figure

73.

16-Bit Capture Mode

Capture mode has two options that are selected by Bit EXEN2

in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter

that, upon overflowing, sets bit TF2, the Timer 2 overflow bit,

which can be used to generate an interrupt. If EXEN2 = 1,

Timer 2 still performs the above, but a l-to-0 transition on

external input T2EX causes the current value in the Timer 2

registers, TL2 and TH2, to be captured into registers RCAP2L

and RCAP2H, respectively. In addition, the transition at T2EX

causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can

generate an interrupt. Capture mode is shown in Figure 74. The

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