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ADE75 数据表(PDF) 109 Page - Analog Devices |
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ADE75 数据表(HTML) 109 Page - Analog Devices |
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109 / 148 page  Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 109 of 148 TIMERS The ADE75XX/ADE71XX has three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three can be configured to operate either as timers or as event counters. When functioning as a timer, the TLx register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Because a machine cycle on a single-cycle core consists of one core clock period, the maximum count rate is the core clock frequency. When functioning as a counter, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin: T0, T1, or T2. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. Because it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency. There are no restrictions on the duty cycle of the external input signal, but, to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. User configuration and control of all timer operating modes is achieved via the SFRs in Table 96. Table 96. Timer SFRs SFR Address Bit Addressable Description TCON 0x88 Yes Timer0 and Timer1 Control Register – see Table 98 TMOD 0x89 No Timer Mode register– see Table 97 TL0 0x8A No Timer0 LSB– see Table 101 TL1 0x8B No Timer1 LSB– see Table 103 TH0 0x8C No Timer0 MSB– see Table 100 TH1 0x8D No Timer1 MSB– see Table 102 T2CON 0xC8 Yes Timer2 Control Register – see Table 99 RCAP2L 0xCA No Timer2 Reload/Capture LSB – see Table 107 RCAP2H 0xCB No Timer2 Reload/Capture MSB – see Table 106 TL2 0xCC No Timer2 LSB – see Table 105 TH2 0xCD No Timer2 MSB – see Table 104 TIMER SFR REGISTER LIST Table 97. Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89) Bit Location Bit Mnemonic Default Value Description 7 Gate1 0 Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set. 6 C_T1 0 Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select the timer operation (input from internal system clock). Timer 1 Mode Select bits M1 M0 Description 0 0 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 5-4 T1_M1, T1_M0 00 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. |
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