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ADE75 数据表(PDF) 124 Page - Analog Devices |
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ADE75 数据表(HTML) 124 Page - Analog Devices |
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124 / 148 page ![]() ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 124 of 148 cleared, RI is set as soon as the byte of data is received. In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data is received. 4 0x9C REN 0 Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 3 0x9B TB8 0 Serial Port Transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3. 2 0x9A RB8 0 Serial Port Receiver Bit 9. The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. 1 0x99 TI 0 Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. 0 0x98 RI 0 Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by user software. Table 123. Serial port Buffer SFR (SBUF, 0x99) Bit Location Bit Mnemonic Default Value Description 7-0 SBUF 0 Serial port data buffer Table 124. Enhanced Serial baud rate control SFR (SBAUDT, 0x9E) Bit Location Bit Mnemonic Default Value Description 7 OWE 0 Overwrite Error. This bit is set when new data is received and RI=1. It indicates that SBUF was not read before the next character was transferred in, causing the prior SBUF data to be lost. Write a zero to this bit to clear it.. 6 FE 0 Frame Error. This bit is set when the received frame did not have a valid stop bit. This bit is read only and updated every time a frame is received. 5 BE 0 Break Error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission frame, the time required for a start bit, 8 data bits, a parity bit and half a stop bit. This bit is updated every time a frame is received. 4-3 SBTH1, SBTH0 0 Extended divider ratio for baud rate setting as shown in Table 126 2, 1, 0 DIV2, DIV1, DIV0 0 Binary Divider DIV2 DIV1 DIV0 0 0 0 Divide by 1. See Table 126. 0 0 1 Divide by 2. See Table 126. 0 1 0 Divide by 4. See Table 126. 0 1 1 Divide by 8. See Table 126. 1 0 0 Divide by 16. See Table 126. 1 0 1 Divide by 32. See Table 126. 1 1 0 Divide by 64. See Table 126. |
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