ADE75 datasheet(126/148 Pages) AD

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ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 126 of 148

2400

00H

ABH

- 0.31

300

17H

ABH

- 0.31

300

0FH

ABH

- 0.31

300

07H

ABH

- 0.31

300

06H

ABH

- 0.31

300

05H

ABH

- 0.31

300

04H

ABH

- 0.31

300

03H

ABH

- 0.31

300

02H

ABH

- 0.31

UART OPERATION MODES

Mode 0 (Shift Register with baud rate fixed at

Fcore /12)

Mode 0 is selected when the SM0 and SM1 bits in the SCON

SFR are clear. In this shift register mode, serial data enters and

exits through RxD. TxD outputs the shift clock. The baud rate is

fixed at Fcore/12. Eight data bits are transmitted or received.

Transmission is initiated by any instruction that writes to SBUF.

The data is shifted out of the RxD line. The 8 bits are

transmitted with the least significant bit (LSB) first.

Reception is initiated when the receive enable bit (REN) is 1

and the receive interrupt bit (RI) is 0. When RI is cleared, the

data is clocked into the RxD line, and the clock pulses are

output from the TxD line as shown in Figure 76.

RxD

(DATA OUT)

TxD

(SHIFT CLOCK)

DATA BIT 0

DATA BIT 1

DATA BIT 6

DATA BIT 7

Figure 76. 8-Bit Shift Register Mode

Mode 1 (8-Bit UART, Variable Baud Rate)

Mode 1 is selected by clearing SM0 and setting SM1. Each data

byte (LSB first) is preceded by a start bit (0) and followed by a

stop bit (1). Therefore, each frame consists of 10 bits

transmitted on TxD or received on RxD.

The baud rate is set by a timer overflow rate. Timer 1 or Timer 2

can be used to generate baud rates or both timers can be used

simultaneously where one generates the transmit rate and the

other generates the receive rate. There is also a dedicated timer

for baud rate generation, UART Timer, which has a fractional

divisor to precisely generate any baud rate—see the UART

Timer Generated Baud Rates section.

Transmission is initiated by a write to SBUF. Next a stop bit (a

1) is loaded into the 9th bit position of the transmit shift

on TxD and the transmit interrupt flag (TI) is automatically set

as shown in Figure 77.

Figure 77. 8-Bit Variable Baud Rate

Reception is initiated when a 1-to-0 transition is detected on

RxD. Assuming that a valid start bit is detected, character

reception continues. The 8 data bits are clocked into the serial

port shift register.

All of the following conditions must be met at the time the final

shift pulse is generated to receive a character:

•

If the extended UART is disabled (EXTEN=0 in the CFG

SFR), RI must be zero to receive a character. This ensures

that the data in SBUF will not be overwritten if the last

received character has not been read.

•

If frame error checking is enabled by setting SM2, the

received stop bit must be set to receive a character. This

ensures that every character received comes from a valid

frame, with both a start and a stop bit)

If any of these conditions are not met, the received frame is

irretrievably lost, and the receive interrupt flag, RI, is not set.

If the received frame has met the above criteria, the following

events occur:

•

The 8 bits in the receive shift register are latched into SBUF.

•

The 9th bit (stop bit) is clocked into RB8 in SCON.

•

The receiver interrupt flag (RI) is set.

Mode 2 (9- bit UART with baud fixed at Fcore/64

or Fcore/32)

Mode 2 is selected by setting SM0 and clearing SM1. In this

mode, the UART operates in 9-bit mode with a fixed baud rate.

The baud rate is fixed at Fcore/64 by default, although by setting

the SMOD bit in PCON, the frequency can be doubled to

Fcore/32. Eleven bits are transmitted or received: a start bit (0), 8

data bits, a programmable 9th bit, and a stop bit (1). The 9th bit

is most often used as a parity bit or as part of a multiprocessor

communication protocol, although it can be used for anything,

including a ninth data bit if required.

TxD

(SCON.1)

START

BIT

STOP BIT

SET INTERRUPT

I.E., READY FOR MORE DATA

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