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ADE75 数据表(PDF) 130 Page - Analog Devices |
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ADE75 数据表(HTML) 130 Page - Analog Devices |
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130 / 148 page  ADE75xx/ADE71xx Preliminary Technical Data Rev. PrE | Page 130 of 148 SERIAL PERIPHERAL INTERFACE INTERFACE (SPI) The ADE75XX/ADE71XX integrates a complete hardware serial peripheral interface on-chip. The SPI interface is full duplex so that eight bits of data are synchronously transmitted and received simultaneously. This SPI implementation is double buffered. This allows the user to read the last byte of received data while a new byte is shifted in. The next byte to be transmitted can be loaded while the current byte is shifted out. The SPI port can be configured for Master or Slave operation. The physical interface to the SPI is done via MISO (P0.3), MOSI (P0.2), SCLK (P0.4) and SS (P0.5) pins, while the firmware interface is done via the SPI Configuration Register SFR (SPIMOD1, 0xE8) , SPI Configuration Register SFR (SPIMOD2, 0xE9) , SPI Interrupt Status Register SFR (SPISTAT, 0xEA), SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) and SPI Receive Buffer SFR (SPI2CRx, 0x9B) . Note that the SPI pins are shared with the I2C pins. Therefore, the user can enable only one interface at a time. The SCPS bit in the CFG SFR selects which peripheral is active. SPI SFR REGISTER LIST SFR Address Name R/W Length Default Value Description 0x9A SPI2CTx W 8 SPI Data out register 0x9B SPI2CRx R 8 0 SPI Data in register 0xE8 SPIMOD1 R/W 8 0x10 SPI configuration register 0xE9 SPIMOD2 R/W 8 0 SPI configuration register 0xEA SPISTAT R/W 8 0 SPI Interrupt Status register Table 127: SPI SFR register list Table 128. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) Bit Location Bit Mnemonic Default Value Description 7-0 SPI2CTx 0 SPI or I2C transmit buffer When SPI2CTx SFR is written, its content is transfered to the transmit FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus. Table 129. SPI Receive Buffer SFR (SPI2CRx, 0x9B) Bit Location Bit Mnemonic Default Value Description 7-0 SPI2CRx 0 SPI or I2C receive buffer When SPI2CRx SFR is read, one byte from the Receive FIFO output is transfered to SPI2CRx SFR. A new data from the SPI or I2C bus is written to the FIFO input. Table 130. SPI Configuration Register SFR (SPIMOD1, 0xE8) Bit Location Bit Addr. Bit Name Default Value Description 7-5 0xEF – 0xEE Reserved 0 Reserved 5 0xED INTMOD 0 SPI Interrupt mode 0: SPI Interrupt set when SPI Rx buffer full 1: SPI interrupt set when SPI Tx buffer empty 0xEC Master Mode: SS output control. See Figure 82. 0 The SS is held low while this bit is clear. This allows manual chip select control using the SS pin. Single Byte Read or Write: The SS will go low during a single byte transmission and then return high. 4 AUTO_SS 1 1 Continuous Transfer: The SS will go low during the duration of the multi- byte continuous transfer and then return high. 3 0xEB SSE 0 Slave Mode: SS input enable |
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