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ADE75 数据表(PDF) 143 Page - Analog Devices |
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ADE75 数据表(HTML) 143 Page - Analog Devices |
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143 / 148 page ![]() Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 143 of 148 Table 144. Port 0 SFR (P0, 0x80) Note: When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set Bit Location Bit Addr. Bit Name Default Value Description 7 0x87 T1 1 This bit reflects the state of P0.7/SS/T1 pin. It can be written or read. 6 0x86 T0 1 This bit reflects the state of P0.6/SCLK/T0 pin. It can be written or read. 5 0x85 1 This bit reflects the state of P0.5/MISO pin. It can be written or read. 4 0x84 1 This bit reflects the state of P0.4/MOSI/SDATA pin. It can be written or read. 3 0x83 CF2 1 This bit reflects the state of P0.3/CF2 pin. It can be written or read. 2 0x82 CF1 1 This bit reflects the state of P0.2/CF1/RTCCAL pin. It can be written or read. 1 0x81 1 This bit reflects the state of P0.1 pin. It can be written or read. 0 0x80 INT1 1 This bit reflects the state of P0.0/INT1/BCTRL pin. It can be written or read. Table 145. Port 1 SFR (P1, 0x90) Note: When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set Bit Location Bit Addr. Bit Name Default value Description 7 0x97 1 This bit reflects the state of P1.7 pin. It can be written or read. 6 0x96 1 This bit reflects the state of P1.6 pin. It can be written or read. 5 0x95 1 This bit reflects the state of P1.5 pin. It can be written or read. 4 0x94 T2 1 This bit reflects the state of P1.4/T2 pin. It can be written or read. 3 0x93 T2EX 1 This bit reflects the state of P1.3/T2EX pin. It can be written or read. 2 0x92 1 This bit reflects the state of P1.2 pin. It can be written or read. 1 0x91 TxD 1 This bit reflects the state of P1.1/TxD pin. It can be written or read. 0 0x90 RxD 1 This bit reflects the state of P1.0/RxD pin. It can be written or read. Table 146. Port 2 SFR (P2, 0xA0) Note: When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set Bit Location Bit Addr. Bit Name Default Value Description 7 - 2 0x97 – 0x92 0x3F These bits are unused and should be left set 1 0x91 P2.1 1 This bit reflects the state of P2.1 pin. It can be written or read. 0 0x90 P2.0 1 This bit reflects the state of P2.0 pin. It can be written or read. Interrupt pins configuration SFR (INTPR, 0xFF) Bit Location Bit Mnemonic Default Value Description 7 RTCCAL 0 Control RTC calibration output When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window FSEL[1:0] Calibration window, frequency 0 0 30.5 seconds, 1Hz 0 1 30.5 seconds, 512 Hz 1 0 0.244 seconds, 500Hz 6-5 FSEL[1:0] 1 1 0.244 seconds, 16.384 kHz 4 Reserved Controls the function of INT1T 3-1 INT1PRG[2:0] 000 INT1PRG[2:0] Function |
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