R8CSLASH2G datasheet(44/344 Pages) RENESAS

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R8C/2G Group

5. Resets

Rev.1.00

Apr 04, 2008

Page 24 of 318

REJ09B0387-0100

Resets

The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset,

voltage monitor 2 reset, watchdog timer reset, and software reset.

Table 5.1 lists the Reset Names and Sources. Figure 5.1 lists the Block Diagram of Reset Circuit.

Figure 5.1

Block Diagram of Reset Circuit

Table 5.1

Reset Names and Sources

Reset Name

Source

Hardware reset

Input voltage of RESET pin is held “L”

Power-on reset

VCC rises

Voltage monitor 0 reset

VCC falls (monitor voltage: Vdet0)

Voltage monitor 1 reset

VCC falls (monitor voltage: Vdet1)

Voltage monitor 2 reset

VCC falls (monitor voltage: Vdet2)

Watchdog timer reset

Underflow of watchdog timer

Software reset

Write 1 to PM03 bit in PM0 register

RESET

Power-on reset

circuit

Voltage

detection

circuit

Watchdog

timer

CPU

Voltage monitor 0 reset

SFRs

Bits VCA25,

VW0C0, and

VW0C6

SFRs

Bits VCA13, VCA26, VCA27,

VW1C2, VW1C3,

VW2C2, VW2C3,

VW0C1, VW0F0,

VW0F1, and VW0C7

Pin, CPU, and

SFR bits other than

those listed above(1)

VCC

Hardware reset

Power-on reset

Voltage monitor 1 reset

Watchdog timer

reset

Software reset

VCA13: Bit in VCA1 register

VCA25, VCA26, VCA27: Bits in VCA2 register

VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register

VW1C2, VW1C3: Bits in VW1C register

VW2C2, VW2C3: Bits in VW2C register

Voltage monitor 2

reset

SFRs

Bits VCA25,

VW0C0, and

VW0C6

NOTE:

1. The following registers and bits are not reset.

• Registers TRESEC, TREMIN, TREWK, and TRECR2

• Bits PM, H12_H24, and TSTART in the TRECR1 register

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