R8CSLASH2G datasheet(57/344 Pages) RENESAS

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R8C/2G Group

6. Voltage Detection Circuit

Rev.1.00

Apr 04, 2008

Page 37 of 318

REJ09B0387-0100

Figure 6.7

VW1C Register

Voltage Monitor 1 Circuit Control Register (1)

Symbol

Address

After Reset(8)

VW1C

0036h

00001010b

Bit Symbol

Bit Name

Function

NOTES:

9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or

below ). (Do not set to 0.)

Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW1C register.

When the VW1C register is rew ritten, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the

VW1C register.

To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting

Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit

enabled).

Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is

w ritten to it).

The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/reset enabled).

The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).

Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).

To set VW1C0 bit to 1 (enable), follow the procedure show n in Table 6.3 Procedure for Setting Bits

Associated w ith Voltage Monitor 1 Interrupt and Reset.

The VW1C7 bit is enabled w hen the VCAC1 bit in the VCAC register is set to 0 (one edge). Set the VW1C7 bit after

setting the VCAC1 bit to 0.

Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,

or voltage monitor 2 reset.

VW1C7

Voltage monitor 1 interrupt/reset

generation condition select bit(7, 9)

0 : When VCC reaches Vdet1 or above

1 : When VCC reaches Vdet1 or below

VW1C6

Voltage monitor 1 circuit mode

select bit(5)

0 : Voltage monitor 1 interrupt mode

1 : Voltage monitor 1 reset mode

VW1C3

Voltage detection 1 signal monitor

flag(3, 8)

VW1F1

Sampling clock select bits

b5 b4

0 0 : fOCO-S divided by 1

0 1 : fOCO-S divided by 2

1 0 : fOCO-S divided by 4

1 1 : fOCO-S divided by 8

VW1F0

0 : VCC < Vdet1

1 : VCC ≥ Vdet1 or voltage detection 1

circuit disabled

0 : Digital filter enabled mode

(digital filter circuit enabled)

1 : Digital filter disabled mode

(digital filter circuit disabled)

VW1C2

Voltage change detection

flag(3, 4, 8)

VW1C1

Voltage monitor 1 digital filter

disable mode select bit(2)

VW1C0

Voltage monitor 1 interrupt/reset

enable bit(6)

0 : Disable

1 : Enable

b7 b6 b5 b4

0 : Not detected

1 : Vdet1 crossing detected

b1 b0

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