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R8C/2G 数据表(PDF) 63 Page - Renesas Technology Corp

部件名 R8C/2G
功能描述  RENESAS MCU R8C FAMILY / R8C/2x SERIES
PDF  344 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R8C/2G 数据表(HTML) 63 Page - Renesas Technology Corp

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R8C/2G Group
6. Voltage Detection Circuit
Rev.1.00
Apr 04, 2008
Page 43 of 318
REJ09B0387-0100
Figure 6.12
Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
Vdet1
VW1C3 bit
Internal reset signal
(VW1C6 = 1)
VCC
2.2 V(1)
2 cycles of sampling clock of
digital filter
VW1C2 bit
VW1C2 bit
When the VW1C1 bit is set to 1
(digital filter disabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 0
(when VCC reaches Vdet1 or
above)
Set to 0 by interrupt request
acknowledgement
2 cycles of sampling clock of
digital filter
Set to 0 by a program
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by interrupt request
acknowledgement
VW1C2 bit
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
When the VW1C1 bit is set to 0
(digital filter enabled) and the
VCAC1 bit is set to 1 (both edges)
VW1C2 bit
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Voltage monitor 1
interrupt request
(VW1C6 = 0)
When the VW1C1 bit is set to 0
(digital filter enabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 0
(when VCC reaches Vdet1 or
above)
Internal reset signal
(VW1C6 = 1)
VW1C2 bit
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
When the VW1C1 bit is set to 0
(digital filter enabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 1
(when VCC reaches Vdet1 or
below)
Set to 0 by a program
Internal reset signal
(VW1C6 = 1)
VW1C2 bit
Voltage monitor 1
interrupt request
(VW1C6 = 0)
When the VW1C1 bit is set to 1
(digital filter disabled) and the
VCAC1 bit is set to 1 (both edges)
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
When the VW1C1 bit is set to 1
(digital filter disabled), and the
VCAC1 bit is set to 0 (one edge),
and the VW1C7 bit is set to 1
(when VCC reaches Vdet1 or
below)
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)
NOTE:
1. If voltage monitor 0 reset is not used, set the power supply to VCC
≥ 2.2.
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
0
1
0
1
0
1
0
1
0
1
0
1
0
1



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