R8CSLASH2G datasheet(92/344 Pages) RENESAS

92 / 344 page

R8C/2G Group

8. I/O Ports

Rev.1.00

Apr 04, 2008

Page 72 of 318

REJ09B0387-0100

Figure 8.6

Pi (i = 0, 1, 3, 4, or 6) Register

Port Pi Register (i = 0, 1, 3, 4, or 6)(1, 2, 3)

Symbol

Address

After Reset

00E0h

00h

00E1h

00h

00E5h

00h

00E8h

00h

00ECh

00h

Bit Symbol

Bit Name

Function

NOTES:

Bits P4_0 to P4_2, P4_6, and P4_7 in the P4 register are unavailable on this MCU.

If it is necessary to set bits P4_0 to P4_2, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0.

Bits P6_1, P6_2, and P6_7 in the P6 register are unavailable on this MCU.

If it is necessary to set bits P6_1, P6_2, and P6_7, set to 0 (“L” level). When read, the content is 0.

Pi_7

Pi_6

Bits P0_0 to P0_3 in the P0 register are unavailable on this MCU.

If it is necessary to set bits P0_0 to P0_3, set to 0 (“L” level). When read, the content is 0.

b3 b2 b1 b0

Pi_1

Pi_5

Pi_0

Pi_2

Pi_4

Pi_3

b7 b6 b5 b4

Port Pi_0 bit

Port Pi_1 bit

Port Pi_7 bit

Port Pi_5 bit

Port Pi_4 bit

Port Pi_3 bit

Port Pi_6 bit

Port Pi_2 bit

The pin level of any I/O port w hich is set

to input mode can be read by reading the

corresponding bit in this register. The pin

level of any I/O port w hich is set to output

mode can be controlled by w riting to the

corresponding bit in this register.

0 : “L” level

1 : “H” level

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