R8CSLASH2G datasheet(45/344 Pages) RENESAS

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R8C/2G Group

5. Resets

Rev.1.00

Apr 04, 2008

Page 25 of 318

REJ09B0387-0100

Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after

Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.

Figure 5.2

CPU Register Status after Reset

Figure 5.3

Reset Sequence

Table 5.2

Pin Functions while RESET Pin Level is “L”

Pin Name

Pin Functions

P0_4 to P0_7

Input port

P1, P3

Input port

P4_3, P4_5

Input port

P4_4

Output port

P6_0, P6_3 to P6_6

Input port

b19

Interrupt table register(INTB)

Program counter(PC)

User stack pointer(USP)

Interrupt stack pointer(ISP)

Static base register(SB)

Content of addresses 0FFFEh to 0FFFCh

Flag register(FLG)

IPL

b15

0000h

Data register(R0)

Data register(R1)

Data register(R2)

Data register(R3)

Address register(A0)

Address register(A1)

Frame base register(FB)

00000h

0000h

Start time of flash memory

(CPU clock

× 14 cycles)

0FFFCh

0FFFEh

0FFFDh

Content of reset vector

CPU clock

Address

(internal address

signal)

NOTES:

1. Hardware reset.

2. When the “L” input width to the RESET pin is set to fOCO-S clock

× 32 cycles or more, setting the RESET pin to “H” also sets the internal

reset signal to “H” at the same.

CPU clock

× 28 cycles

fOCO-S clock

× 32 cycles(2)

fOCO-S

Internal reset

signal

RESET pin

10 cycles or more are needed(1)

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