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R8C/2G 数据表(PDF) 85 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 85 Page - Renesas Technology Corp |
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85 / 344 page ![]() R8C/2G Group 8. I/O Ports Rev.1.00 Apr 04, 2008 Page 65 of 318 REJ09B0387-0100 8. I/O Ports There are 27 I/O ports P0_4 to P0_7, P1, P3, P4_3, P4_5, P6_0, P6_3 to P6_6. When the XCIN clock oscillation circuit is not used, P4_3 can be used as an I/O port and P4_4 can be used as an output port. Table 8.1 lists an Overview of I/O Ports. NOTES: 1. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR0 register. 2. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR1 register. 3. Do not use port P4_4 as an input port (input mode). 8.1 Functions of I/O Ports The PDi_j (j = 0 to 7) bit in the PDi (i = 0, 1, 3, 4, 6) register controls I/O of the ports P0_4 to P0_7, P1, P3, P4_3 to P4_5, P6_0, P6_3 to P6_6. The Pi register consists of a port latch to hold output data and a circuit to read pin states. Figures 8.1 to 8.3 show the Configurations of I/O Ports. Table 8.2 lists the Functions of I/O Ports. Also, Figure 8.5 shows the PDi (i = 0, 1, 3, 4, or 6) Register. Figure 8.6 shows the Pi (i = 0, 1, 3, 4, or 6) Register, Figure 8.7 shows Registers PINSR2, PINSR3, and PINSR4, Figure 8.8 shows the PMR Register, Figure 8.9 shows Registers PUR0 and PUR1. i = 0, 1, 3, 4, 6, j = 0 to 7 NOTE: 1. Nothing is assigned to bits PD0_0 to PD0_3, PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2, PD6_7. Table 8.1 Overview of I/O Ports Ports I/O Type of Output I/O Setting Internal Pull-Up Resister P0_4 to P0_7, P1, P3 I/O CMOS3 State Set per bit Set every 4 bits(1) P4_3 I/O CMOS3 State Set per bit Set every bit(2) P4_4 Output CMOS3 State Set per bit(3) None P4_5 I/O CMOS3 State Set per bit Set every bit(2) P6_0, P6_3 I/O CMOS3 State Set per bit Set every 2 bits(2) P6_4 to P6_6 I/O CMOS3 State Set per bit Set every 3 bits(2) Table 8.2 Functions of I/O Ports Operation When Accessing Pi Register Value of PDi_j Bit in PDi Register(1) When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode) Reading Read pin input level Read the port latch Writing Write to the port latch Write to the port latch. The value written to the port latch is output from the pin. |
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