R8CSLASH2G datasheet(79/344 Pages) RENESAS

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R8C/2G Group

7. Comparator

Rev.1.00

Apr 04, 2008

Page 59 of 318

REJ09B0387-0100

7.4.2

Comparator 2

Table 7.4 lists the Procedure for Setting Bits Associated with Comparator 2 Interrupt, Figure 7.14 shows an

Operating Example of Comparator 2 (When Digital Filter Enabled), and Figure 7.15 shows an Operating

Example of Comparator 2 (When Digital Filter Disabled).

NOTE:

1. When the VW2C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction).

Table 7.4

Procedure for Setting Bits Associated with Comparator 2 Interrupt

Step

When Using Digital Filter

When Not Using Digital Filter

Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2)

Set the VCAB6 bit in the VCAB register to 1 (VCMP2 pin input voltage)

Set the VCA27 bit in the VCA2 register to 1 (comparator 2 circuit enabled)

Wait for td(E-A)

Select the interrupt type by the IRQ2SEL bit in the ALCMR register

Select the sampling clock by bits VW2F0

and VW2F1 in the VW2C register

Set the VW2C1 bit in the VW2C register to 1 (digital

filter disabled)

7(1)

Set the VW2C1 bit in the VW2C register

to 0 (digital filter enabled)

−

Select the interrupt request timing by the VCAC2 bit in the VCAC register and the VW2C7 bit in

the VW2C register

Set the VW2C2 bit in the VW2C register to 0

Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on)

−

Wait for 2 cycles of the sampling clock of

the digital filter.

− (No wait time required)

Set the VW2C0 bit in the VW2C register to 1 (comparator 2 interrupt enabled)

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