R8CSLASH2G datasheet(80/344 Pages) RENESAS

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R8C/2G Group

7. Comparator

Rev.1.00

Apr 04, 2008

Page 60 of 318

REJ09B0387-0100

Figure 7.14

Operating Example of Comparator 2 (When Digital Filter Enabled)

Reference voltage

VCA13 bit

VCOUT2 output

(LCM2POR = 0)

VCMP2

The above applies under the following conditions.

• VCA27 bit in VCA2 register = 1 (comparator 2 circuit enabled)

• VW2C0 bit in VW2C register = 1 (comparator 2 interrupt enabled)

• CM2OE bit in ALCMR register = 1 (output enabled)

• VCAB6 bit in VCAB register = 1 (VCMP2 pin input)

• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)

2 cycles of sampling clock

of digital filter

VW2C2 bit

VCA13: Bit in VCA1 register

VW2C1, VW2C2, VW2C7: Bits in VW2C register

VCAC2: Bit in VCAC register

LCM2POR, IRQ2SEL: Bits in ALCMR register

2 cycles of sampling clock

of digital filter

IR bit in

VCMP2IC register

(IRQ2SEL = 1)

When the VW2C1 bit is set to 0

(digital filter enabled) and the

VCAC2 bit is set to 1 (both edges)

VW2C2 bit

When the VW2C1 bit is set to 0

(digital filter enabled), the VCAC2

bit is set to 0 (one edge), and

the VW2C7 bit is set to 0 (VCMP2

reaches reference voltage or above)

VW2C2 bit

When the VW2C1 bit is set to 0

(digital filter enabled), the VCAC2

bit is set to 0 (one edge), and

the VW2C7 bit is set to 1 (VCMP2

reaches reference voltage or below)

IR bit in

VCMP2IC register

(IRQ2SEL = 1)

VCOUT2 output

(LCM2POR = 0)

IR bit in

VCMP2IC register

(IRQ2SEL = 1)

VCOUT2 output

(LCM2POR = 1)

Set to 0 by interrupt request

acknowledgement, or by a program

Set to 0 by a program

Set to 0 by interrupt request

acknowledgement, or by a program

Set to 0 by interrupt request

acknowledgement, or by a program

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