R8CSLASH2G datasheet(51/344 Pages) RENESAS

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R8C/2G Group

5. Resets

Rev.1.00

Apr 04, 2008

Page 31 of 318

REJ09B0387-0100

5.6

Watchdog Timer Reset

When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,

CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the

reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as

the CPU clock.

The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.

The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.

Refer to 16. Watchdog Timer for details of the watchdog timer.

5.7

Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The

program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip

oscillator clock divided by 8 is automatically selected for the CPU clock.

The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.

The internal RAM is not reset.

R8C/2G 数据表(PDF) 51 Page - Renesas Technology Corp