R8CSLASH2G datasheet(82/344 Pages) RENESAS

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R8C/2G Group

7. Comparator

Rev.1.00

Apr 04, 2008

Page 62 of 318

REJ09B0387-0100

7.5

Comparator 1 and Comparator 2 Interrupts

Two interrupt requests are generated, one each for comparator 1 and comparator 2. Non-maskable or maskable can

be selected for each interrupt type. Refer to 13. Interrupts for interrupts.

7.5.1

Non-Maskable Interrupts

When IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 0, the comparator i interrupt functions as a non-

maskable interrupt. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is

set to 1. At this time, a non-maskable interrupt request for comparator i is generated.

7.5.2

Maskable Interrupts

When the IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 1, the comparator i interrupt functions as a

maskable interrupt. The comparator i interrupt uses the single VCMPiIC register (bits IR and ILVL0 to ILVL2)

and a single vector. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is

set to 1. At this time, the IR bit in the VCMPiIC register is set to 1 (interrupt requested).

Refer to 13.1.6 Interrupt Control for the VCMPiIC register and 13.1.5.2 Relocatable Vector Tables for

interrupt vectors.

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