R8CSLASH2G datasheet(77/344 Pages) RENESAS

77 / 344 page

R8C/2G Group

7. Comparator

Rev.1.00

Apr 04, 2008

Page 57 of 318

REJ09B0387-0100

Figure 7.12

Operating Example of Comparator 1 (When Digital Filter Enabled)

Reference voltage

VW1C3 bit

VCOUT1 output

(LCM1POR = 0)

VCMP1

The above applies under the following conditions.

• VCA26 bit in VCA2 register = 1 (comparator 1 circuit enabled)

• VW1C0 bit in VW1C register = 1 (comparator 1 interrupt enabled)

• CM1OE bit in ALCMR register = 1 (output enabled)

• VCAB5 bit in VCAB register = 1 (VCMP1 pin input)

• COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected)

2 cycles of sampling clock

of digital filter

VW1C2 bit

VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register

VCAC1: Bit in VCAC register

LCM1POR, IRQ1SEL: Bits in ALCMR register

2 cycles of sampling clock

of digital filter

IR bit in

VCMP1IC register

(IRQ1SEL = 1)

When the VW1C1 bit is set to 0

(digital filter enabled) and the

VCAC1 bit is set to 1 (both edges)

VW1C2 bit

Set to 0 by a program

When the VW1C1 bit is set to 0

(digital filter enabled), the VCAC1

bit is set to 0 (one edge), and

the VW1C7 bit is set to 0 (VCMP1

reaches reference voltage or above)

VW1C2 bit

When the VW1C1 bit is set to 0

(digital filter enabled), the VCAC1

bit is set to 0 (one edge), and

the VW1C7 bit is set to 1 (VCMP1

reaches reference voltage or below)

Set to 0 by a program

IR bit in

VCMP1IC register

(IRQ1SEL = 1)

Set to 0 by interrupt request

acknowledgement, or by a program

VCOUT1 output

(LCM1POR = 0)

IR bit in

VCMP1IC register

(IRQ1SEL = 1)

Set to 0 by interrupt request

acknowledgement, or by a program

VCOUT1 output

(LCM1POR = 1)

Set to 0 by interrupt request

acknowledgement, or by a program

Set to 0 by a program

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