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R8C/2G 数据表(PDF) 46 Page - Renesas Technology Corp

部件名 R8C/2G
功能描述  RENESAS MCU R8C FAMILY / R8C/2x SERIES
PDF  344 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R8C/2G 数据表(HTML) 46 Page - Renesas Technology Corp

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R8C/2G Group
5. Resets
Rev.1.00
Apr 04, 2008
Page 26 of 318
REJ09B0387-0100
Figure 5.4
OFS Register
Option Function Select Register(1)
Symbol
Address
When Shipping
OFS
0FFFFh
FFh(3)
Bit Symbol
Bit Name
Function
RW
NOTES:
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
(b6)
Reserved bit
Set to 1.
RW
CSPROINI
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
RW
Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
ROMCP1
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
ROMCR
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
RW
(b1)
RW
Reserved bit
Set to 1.
WDTON
RW
Watchdog timer start
select bit
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
1
11
b7 b6 b5 b4 b3 b2 b1 b0
(b4)
Reserved bit
Set to 1.
RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
LVD0ON
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW



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