R8CSLASH2G datasheet(61/344 Pages) RENESAS

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R8C/2G Group

6. Voltage Detection Circuit

Rev.1.00

Apr 04, 2008

Page 41 of 318

REJ09B0387-0100

6.2

Voltage Monitor 0 Reset

Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset and Figure 6.11 shows an

Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the

VW0C1 bit in the VW0C register to 1 (digital filter disabled).

NOTE:

1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction).

Figure 6.11

Example of Voltage Monitor 0 Reset Operation

Table 6.2

Procedure for Setting Bits Associated with Voltage Monitor 0 Reset

Step

When Using Digital Filter

When Not Using Digital Filter

Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled)

Wait for td(E-A)

Select the sampling clock of the digital filter

by the VW0F0 to VW0F1 bits in the VW0C

Set the VW0C7 bit in the VW0C register to

4(1)

Set the VW0C1 bit in the VW0C register to

0 (digital filter enabled)

Set the VW0C1 bit in the VW0C register to

1 (digital filter disabled)

5(1)

Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode)

Set the VW0C2 bit in the VW0C register to 0

Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on)

−

Wait for 4 cycles of the sampling clock of

the digital filter

− (No wait time required)

Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)

Vdet0

Internal reset signal

VCC

The above applies under the following conditions.

• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)

• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)

• VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode)

When the internal reset signal is held “L”, the pins, CPU and SFR are reset.

The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by

the reset vector.

Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.

fOCO-S

× 32

Sampling clock of

digital filter

× 4 cycles

When the VW0C1 bit is set

to 0 (digital filter enabled)

Internal reset signal

When the VW0C1 bit is set

to 1 (digital filter disabled)

and the VW0C7 bit is set

to 1

fOCO-S

× 32

VW0C1 and VW0C7: Bits in VW0C register

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