R8CSLASH2G datasheet(30/344 Pages) RENESAS

部件名	R8C/2G

功能描述	RENESAS MCU R8C FAMILY / R8C/2x SERIES

PDF	344 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

30 / 344 page

R8C/2G Group

2. Central Processing Unit (CPU)

Rev.1.00

Apr 04, 2008

Page 10 of 318

REJ09B0387-0100

2.8.7

Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8

Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10

Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/2G 数据表(PDF) 30 Page - Renesas Technology Corp