R8CSLASH2G datasheet(56/344 Pages) RENESAS

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R8C/2G Group

6. Voltage Detection Circuit

Rev.1.00

Apr 04, 2008

Page 36 of 318

REJ09B0387-0100

Figure 6.6

VW0C Register

Voltage Monitor 0 Circuit Control Register (1)

Symbol

Address

VW0C

0038h

Bit Symbol

Bit Name

Function

NOTES:

The LVD0ON bit in the OFS register is

set to 1 and hardw are reset

: 1000X010b

Pow er-on reset, voltage monitor 0 reset

or LVD0ON bit in the OFS register is set

to 0, and hardw are reset

: 1100X011b

After Reset(2)

Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW0C register.

The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage

monitor 2 reset.

VW0C6

Voltage monitor 0 circuit

mode select bit

When the VW0C0 bit is set to 1 (voltage monitor 0

reset enabled), set to 1.

—

(b3)

Reserved bit

The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled).

Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).

To set VW0C0 bit to 1 (enable), follow the procedure show n in Table 6.2 Procedure for Setting Bits

Associated w ith Voltage Monitor 0 Reset.

VW0C7

Voltage monitor 0 reset

generation condition select

bit(4)

When the VW0C1 bit is set to 1 (digital filter

disabled mode), set to 1.

VW0F1

Sampling clock select bits

b5 b4

0 0 : fOCO-S divided by 1

0 1 : fOCO-S divided by 2

1 0 : fOCO-S divided by 4

1 1 : fOCO-S divided by 8

VW0F0

When read, the content is undefined.

0 : Digital filter enabled mode

(digital filter circuit enabled)

1 : Digital filter disabled mode

(digital filter circuit disabled)

VW0C2

Reserved bit

VW0C1

Voltage monitor 0 digital filter

disable mode select bit

VW0C0

Voltage monitor 0 reset

enable bit(3)

0 : Disable

1 : Enable

b7 b6 b5 b4

The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).

b3 b2

Set to 0.

b1 b0

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