R8CSLASH2G datasheet(149/344 Pages) RENESAS

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R8C/2G Group

13. Interrupts

Rev.1.00

Apr 04, 2008

Page 129 of 318

REJ09B0387-0100

13.5

Notes on Interrupts

13.5.1

Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads

interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At

this time, the acknowledged interrupt IR bit is set to 0.

If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the

enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be

generated.

13.5.2

SP Setting

Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an

interrupt is acknowledged before setting a value in the SP, the program may run out of control.

13.5.3

External Interrupt and Key Input Interrupt

Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input

to pins INT0, INT1, INT2, INT4 and pins KI0 to KI3, regardless of the CPU clock.

For details, refer to Table 22.17 (VCC = 5V), Table 22.23 (VCC = 3V), and Table 22.29 (VCC = 2.2V)

External Interrupt INTi (i = 0, 1, 2, 4) Input.

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