R8CSLASH2G datasheet(180/344 Pages) RENESAS

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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 160 of 318

REJ09B0387-0100

17.1.6

Notes on Timer RA

• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the

count starts.

• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by

the MCU. Consequently, the timer value may be updated during the period when these two registers are

being read.

• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by

writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the

READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0

although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or

TUNDF bit which is not supposed to be set to 0 with the MOV instruction.

• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and

TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.

• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.

• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler

immediately after the count starts, then set the TEDGF bit to 0.

• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1

(count starts) while the count is stopped.

During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA

starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).

The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count

stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.

During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.

NOTE:

1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.

• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow

three or more cycles of the count source clock for each write interval.

• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three

or more cycles of the prescaler underflow for each write interval.

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