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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 378 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 378 Page - Renesas Technology Corp |
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378 / 750 page  Section 9 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Jun. 03, 2008 Page 330 of 698 REJ09B0074-0600 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 9.42 shows the timing for status flag clearing by the CPU, and figure 9.43 shows the timing for status flag clearing by the DMAC. T 1 T 2 TSR write cycle TSR address φ Address Write signal Status flag Interrupt request signal Figure 9.42 Timing for Status Flag Clearing by CPU Interrupt request signal Status flag Address Source address DMAC read cycle T 1 T 2 Destination address T 1 T 2 DMAC write cycle φ Figure 9.43 Timing for Status Flag Clearing by DMAC Activation |
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