H8SSLASH2218 datasheet(382/750 Pages) RENESAS

部件名	H8S/2218

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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382 / 750 page

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 334 of 698

REJ09B0074-0600

Contention between Buffer Register Write and Compare Match: If a compare match occurs in

the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the

data prior to the write. Figure 9.48 shows the timing in this case.

Compare

match signal

Write signal

Address

Buffer register

address

Buffer

TGR write cycle

TGR

Buffer register write data

Figure 9.48 Contention between Buffer Register Write and Compare Match

Contention between TGR Read and Input Capture: If the input capture signal is generated in

the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.

Figure 9.49 shows the timing in this case.

Input capture

signal

Read signal

Address

TGR address

TGR

TGR read cycle

Internal

data bus

Figure 9.49 Contention between TGR Read and Input Capture

H8S/2218 数据表(PDF) 382 Page - Renesas Technology Corp