H8SSLASH2218 datasheet(379/750 Pages) RENESAS

379 / 750 page

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Jun. 03, 2008 Page 331 of 698

REJ09B0074-0600

9.8

Usage Notes

Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of

single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not

operate properly with a narrower pulse width. In phase counting mode, the phase difference and

overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at

least 2.5 states. Figure 9.44 shows the input clock conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width

Notes: Phase difference and overlap

Pulse width

: 1.5 states or more

: 2.5 states or more

Figure 9.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in

the final state in which it matches the TGR value (the point at which the count value matched by

TCNT is updated). Consequently, the actual counter frequency is given by the following formula:

f = ————

(N + 1)

Where f : Counter frequency

φ : Operating frequency

N : TGR set value

H8S/2218 数据表(PDF) 379 Page - Renesas Technology Corp

H8S/2218 数据表(HTML) 379 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载