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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 384 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 384 Page - Renesas Technology Corp |
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384 / 750 page  Section 9 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Jun. 03, 2008 Page 336 of 698 REJ09B0074-0600 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.51 shows the timing in this case. Input capture signal Write signal Address φ TCNT Buffer register write cycle T 1 T 2 N TGR N M M Buffer register Buffer register address Figure 9.51 Contention between Buffer Register Write and Input Capture Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Counter clearing signal TCNT input clock φ TCNT TGF flag Prohibited TCFV flag H'FFFF H'0000 Figure 9.52 Contention between Overflow and Counter Clearing |
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