H8SSLASH2218 datasheet(516/750 Pages) RENESAS

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Section 14 Universal Serial Bus (USB)

Rev.6.00 Jun. 03, 2008 Page 468 of 698

REJ09B0074-0600

• USB endpoint receive data size register 2 (UESZ2) [for Bulk_out data reception]

• USB interrupt flag register 0 (UIFR0)

• USB interrupt flag register 1 (UIFR1)

• USB interrupt flag register 3 (UIFR3)

• USB interrupt enable register 0 (UIER0)

• USB interrupt enable register 1 (UIER1)

• USB interrupt enable register 3 (UIER3)

• USB interrupt select register 0 (UISR0)

• USB interrupt select register 1 (UISR1)

• USB interrupt select register 3 (UISR3)

• USB data status register (UDSR)

• USB Configuration value register (UCVR)

• USB test register 0 (UTSTR0)

• USB test register 1 (UTSTR1)

• USB test registers 2 and A to F (UTSTR2, UTSTRA to UTSTRF)

• Module stop control register B (MSTPCRB)

• Extended module stop register (EXMDLSTP)

14.3.1

USB Control Register (UCTLR)

UCTLR is used to select the USB operation clock and control the USB module internal reset.

UCTLR can be read from or written to even when the USB module stop 2 bit (MSTPB0) in

MSTPCRB is 1. For details on UCTLR setting procedure, refer to section 14.5, Communication

Operation.

Bit

Bit Name

Initial Value

R/W

Description

—

R/W

Reserved

The write value should always be 0.

TMOWE

R/W

TMOW Pin Enable

0: The USPND/TMOW pin outputs USPND of USB.

1: The USPND/TMOW pin outputs TMOW of RTC.

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