H8SSLASH2218 datasheet(112/750 Pages) RENESAS

112 / 750 page

Section 2 CPU

Rev.6.00 Jun. 03, 2008 Page 64 of 698

REJ09B0074-0600

2.8

Processing States

The H8S/2000 CPU has five main processing states: the reset state, exception handling state,

program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state

transitions.

• Reset State

In this state the CPU and internal peripheral modules are all initialized and stop. When the

RES

input goes low all current processing stops and the CPU enters the reset state. All interrupts are

masked in the reset state. Reset exception handling starts when the

RES signal changes from

low to high. For details, refer to section 4, Exception Handling.

The reset state can also be entered by a watchdog timer overflow.

• Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.

The CPU fetches a start address (vector) from the exception vector table and branches to that

address. For further details, refer to section 4, Exception Handling.

• Program Execution State

In this state the CPU executes program instructions in sequence.

• Bus-Released State

In a product which has a bus master other than the CPU, such as a direct memory access

controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when the

bus has been released in response to a bus request from a bus master other than the CPU. While

the bus is released, the CPU halts operations.

• Power-Down State

This is a power-down state in which the CPU stops operating. The program stop state occurs

when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,

refer to section 20, Power-Down Modes.

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