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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 215 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 215 Page - Renesas Technology Corp |
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215 / 750 page  Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 167 of 698 REJ09B0074-0600 Bit Bit Name Initial Value R/W Description 10 to 8 ⎯ All 0 R/W Reserved Although these bits are readable/writable, only 0 should be written to. • Full Address Mode (DMACRB) Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. 6 5 DAID DAIDE 0 0 R/W R/W Destination Address Increment/Decrement Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARB is fixed 01: MARB is incremented after a data transfer • When DTSZ = 0, MARB is incremented by 1 after a transfer • When DTSZ = 1, MARB is incremented by 2 after a transfer 10: MARB is fixed 11: MARB is decremented after a data transfer • When DTSZ = 0, MARB is decremented by 1 after a transfer • When DTSZ = 1, MARB is decremented by 2 after a transfer 4 ⎯ 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. |
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