H8SSLASH2218 datasheet(214/750 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 166 of 698

REJ09B0074-0600

• Full Address Mode (DMACRA)

Bit Bit Name Initial Value

R/W

Description

15 DTSZ

R/W

Data Transfer Size

Selects the size of data to be transferred at one time.

0: Byte-size transfer

1: Word-size transfer

SAID

SAIDE

R/W

Source Address Increment/Decrement

Source Address Increment/Decrement Enable

These bits specify whether source address register MARA is

to be incremented, decremented, or left unchanged, when

data transfer is performed.

00: MARA is fixed

01: MARA is incremented after a data transfer

• When DTSZ = 0, MARA is incremented by 1 after a

transfer

• When DTSZ = 1, MARA is incremented by 2 after a

transfer

10: MARA is fixed

11: MARA is decremented after a data transfer

• When DTSZ = 0, MARA is decremented by 1 after a

transfer

• When DTSZ = 1, MARA is decremented by 2 after a

transfer

BLKDIR

BLKE

R/W

Block Direction

Block Enable

These bits specify whether normal mode or block transfer

mode is to be used. If block transfer mode is specified, the

BLKDIR bit specifies whether the source side or the

destination side is to be the block area.

00: Transfer in normal mode

01: Transfer in block transfer mode, destination side is block

area

10: Transfer in normal mode

11: Transfer in block transfer mode, source side is block area

For operation in normal mode and block transfer mode, see

section 7.4, Operation.

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