H8SSLASH2218 datasheet(227/750 Pages) RENESAS

部件名	H8S/2218

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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227 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 179 of 698

REJ09B0074-0600

Address T

Address B

Transfer

IOAR

1 byte or word transfer performed in

response to 1 transfer request

Notes:

Address

Where:

T = L

B = L + (–1)DTID · (2DTSZ · (N–1))

L = Value set in MAR

N = Value set in ETCR

Figure 7.2 Operation in Sequential Mode

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a

transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If

the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU. The maximum number

of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist

of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and

TPU channel 0 to 2 compare match/input capture A interrupts. Figure 7.3 shows an example of the

setting procedure for sequential mode.

H8S/2218 数据表(PDF) 227 Page - Renesas Technology Corp