H8SSLASH2218 datasheet(230/750 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 182 of 698

REJ09B0074-0600

Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission

complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture

A interrupts. Figure 7.5 shows an example of the setting procedure for idle mode.

Idle mode setting

Set DMABCRH

Set transfer source

and transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Idle mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set ech bit in DMABCRH.

· Clear the FAE bit to 0 to select short address

mode.

· Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address and transfer

destinatiln address in MAR and IOAR.

[3] Set the number of transfers in ETCR.

[4] Set each bit in DMACR.

· Set the transfer data size with the DTSZ bit.

· Specify whether MAR is to be incremented or

decremented with the DTID bit.

· Set the RPE bit to 1.

· Specify the transfer direction with the DTDIR

bit.

· Select the activation source with bits DTF3 to

DTF0.

[5] Read the DTE bit in DMABCRL as 0.

[6] Set each bit in DMABCRL.

· Set the DTIE bit to 1.

· Set the DTE bit to 1 to enable transfer.

Figure 7.5 Example of Idle Mode Setting Procedure

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