H8SSLASH2218 datasheet(231/750 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 183 of 698

REJ09B0074-0600

7.4.4

Repeat Mode

Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to

0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer

request, and this is executed the number of times specified in ETCR. On completion of the

specified number of transfers, MAR and ETCRL are automatically restored to their original

settings and operation continues. One address is specified by MAR, and the other by IOAR. The

transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register

functions in repeat mode.

Table 7.5

Function

DTDIR = 0

DTDIR = 1

Initial Setting

Operation

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Incremented/decrem

ented every transfer.

Initial setting is

restored when value

reaches H'0000

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

ETCRH

Holds number of transfers

Number of transfers Fixed

ETCRL

Transfer counter

Number of transfers Decremented every

transfer. Loaded

with ETCRH value

when count reaches

H'00

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the

lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of

transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when

H'00 is set in both ETCRH and ETCRL, is 256.

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