H8SSLASH2225 datasheet(359/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 273 of 982

REJ09B0054-0500

If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on

completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the

CPU.

The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.

Figure 8.34 shows the procedure for continuing transfer when it has been interrupted by an NMI

interrupt on a channel designated for burst mode transfer.

Resumption of

transfer on interrupted

channel

Set DTME bit to 1

Transfer continues

[1]

[2]

DTE = 1

DTME = 0

Transfer ends

Yes

[1]

[2]

Check that DTE = 1 and

DTME = 0 in DMABCRL.

Write 1 to the DTME bit.

Figure 8.34 Example of Procedure for Continuing Transfer on Channel Interrupted by

NMI Interrupt

8.5.14

Forced Termination of DMAC Operation

If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops

on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the

DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL.

Figure 8.35 shows the procedure for forcibly terminating DMAC operation by software.

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