H8SSLASH2225 datasheet(362/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 276 of 982

REJ09B0054-0500

8.7

Usage Notes

8.7.1

DMAC Register Access during Operation

Except for forced termination of the DMAC, the operating (including transfer waiting state)

channel setting should not be changed. The operating channel setting should only be changed

when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.

DMAC register reads during operation (including the transfer waiting state) are described below.

• DMAC control starts one cycle before the bus cycle, with output of the internal address.

Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 8.38 shows an

example of the update timing for DMAC registers in dual address transfer mode.

[1]

Transfer source address register MAR operation (incremented/decremented/fixed)

Transfer counter ETCR operation (decremented)

Block size counter ETCR operation (decremented in block transfer mode)

[2]

Transfer destination address register MAR operation (incremented/decremented/fixed)

[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)

Block transfer counter ETCR operation (decremented, in last transfer cycle of

a block in block transfer mode)

[3]

Transfer address register MAR restore operation (in block or repeat transfer mode)

Transfer counter ETCR restore (in repeat transfer mode)

Block size counter ETCR restore (in block transfer mode)

Note: In single address transfer mode, the update timing is the same as [1].

The MAR operation is post-incrementing/decrementing of the DMA internal address value.

[1]

DMA transfer cycle

DMA read

DMA write

DMA

dead

DMA Internal

address

DMA control

DMA register

operation

DMA last transfer cycle

Transfer

destination

Transfer

destination

Transfer

source

Transfer

source

Idle

Read

Dead

Write

[2]

[1]

[2']

[3]

Figure 8.38 DMAC Register Update Timing

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