H8SSLASH2225 datasheet(368/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 282 of 982

REJ09B0054-0500

Internal address bus

Interrupt controller

Interrupt

request

DTC

On-chip

RAM

Internal data bus

CPU interrupt

request

MRA, MRB:

CRA, CRB:

SAR:

DAR:

DTCERA to DTCERG

and DTCERI:

DTVECR:

DTC mode registers A and B

DTC transfer count registers A and B

DTC source address register

DTC destination address register

DTC enable registers A to G and I

DTC vector register

Legend:

Figure 9.1 Block Diagram of DTC

9.2

The DTC has the following registers.

• DTC mode register A (MRA)

• DTC mode register B (MRB)

• DTC source address register (SAR)

• DTC destination address register (DAR)

• DTC transfer count register A (CRA)

• DTC transfer count register B (CRB)

These six registers cannot be directly accessed from the CPU.

When activated, the DTC reads a set of register information that is stored in on-chip RAM to the

corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated

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