H8SSLASH2225 datasheet(532/1071 Pages) RENESAS

532 / 1071 page

Section 12 8-Bit Timers

Rev. 5.00 Aug 08, 2006 page 446 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

CCLR1

CCLR0

R/W

Counter Clear 1 and 0

These bits select the method by which TCNT is

cleared.

00: Clearing is disabled

01: Cleared on compare-match A

10: Cleared on compare-match B

11: Cleared on rising edge of external reset input

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

The input clock can be selected from three clocks

divided from the system clock (

φ). When use of an

external clock is selected, three types of count can be

selected: at the rising edge, the falling edge, and both

rising and falling edges.

000: Clock input disabled

001:

φ /8 internal clock source, counted on the falling

edge

010:

φ /64 internal clock source, counted on the falling

edge

011:

φ /8192 internal clock source, counted on the

falling edge

100: For channel 0:

Counted on TCNT1 overflow signal*

For channel 1:

Counted on TCNT0 compare-match A*

For channel 2:*

Counted on TCNT3 overflow signal*

For channel 3:*

Counted on TCNT2 compare-match A *

101: External clock source, counted at rising edge

110: External clock source, counted at falling edge

111: External clock source, counted at both rising and

falling edges

Notes: 1. If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and

that of channel 1 (channel 3) is the TCNT1 (TCNT3) compare-match signal, no

incrementing clock will be generated. Do not use this setting.

2. Not available in the H8S/2237 Group and H8S/2227 Group.

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