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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2225 数据表(PDF) 758 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 758 Page - Renesas Technology Corp |
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758 / 1071 page  Section 16 I 2C Bus Interface (IIC) (Option) Rev. 5.00 Aug 08, 2006 page 672 of 982 REJ09B0054-0500 16.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 16.19 shows the IRIC set timing and SCL control. (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL SDA IRIC User processing Write to ICDR (transmit) or read ICDR (receive) Clear IRIC Clear IRIC Clear IRIC 1 A 8 1 1 A 7 1 2 2 2 2 2 2 89 7 (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL SDA IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) SCL SDA IRIC User processing (c) When FS = 1 and FSX = 1 (synchronous serial format) Write to ICDR (transmit) or read ICDR (receive) 8 89 8 7 1 8 7 1 Figure 16.19 IRIC Setting Timing and SCL Control |
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