H8SSLASH2225 datasheet(760/1071 Pages) RENESAS

760 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 674 of 982

REJ09B0054-0500

16.4.9

Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched

internally. Figure 16.20 shows a block diagram of the noise canceler circuit.

The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)

input signal is sampled on the system clock, but is not passed forward to the next circuit unless the

outputs of both latches agree. If they do not agree, the previous value is held.

System clock

period

Sampling clock

Latch

SCL or

SDA input

signal

Match

detector

Internal

SCL or

SDA

signal

Sampling

clock

Figure 16.20 Block Diagram of Noise Canceler

16.4.10 Initialization of Internal State

The IIC has a function for forcible initialization of its internal state if a deadlock occurs during

communication.

Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)

clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 16.3.8, DDC

Switch Register (DDCSWR).

Scope of Initialization: The initialization executed by this function covers the following items:

• TDRE and RDRF internal flags

• Transmit/receive sequencer and internal operating clock counter

• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data

output, etc.)

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