H8SSLASH2225 datasheet(855/1071 Pages) RENESAS

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Section 23 Clock Pulse Generator

Rev. 5.00 Aug 08, 2006 page 769 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

NESEL

R/W

Noise Elimination Sampling Frequency Select

This bit selects the sampling frequency of the

subclock (

φSUB) generated by the subclock oscillator

is sampled by the clock (

φ) generated by the system

clock oscillator

Set 0 when

φ is 5 MHz or higher. Set 1 when φ is 2.1

MHz or lower. Any value can be set when

φ is 2.1 to

5 MHz.

0: Sampling using 1/32

× φ

1: Sampling using 1/4

× φ

SUBSTP

R/W

Subclock Enable

This bit enables/disables subclock generation. This

bit should be set to 1 when subclock is not used.

0: Enables subclock generation.

1: Disables subclock generation.

RFCUT

R/W

Oscillation Circuit Feedback Resistance Control Bit

Selects whether or not built-in feedback resistance

and duty adjustment circuit of the system clock

generator are used when an external clock is input.

Do not access when the crystal resonator is used.

After setting this bit in the external clock input state,

enter software standby mode, watch mode, or

subactive mode. When software standby mode,

watch mode, or subactive mode is entered, switch

whether or not built-in feedback resistance and duty

adjustment circuit are used.

0: Built-in feedback resistance and duty adjustment

circuit of the system clock generator used.

1: Built-in feedback resistance and duty adjustment

circuit of the system clock generator not used.

2—

R/W

Reserved

This bit is readable/writable, but the write value

should always be 0.

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