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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2225 数据表(PDF) 943 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 943 Page - Renesas Technology Corp |
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943 / 1071 page  Section 27 Electrical Characteristics Rev. 5.00 Aug 08, 2006 page 857 of 982 REJ09B0054-0500 (4) Timing of On-Chip Peripheral Modules Table 27.8 lists the timing of on-chip peripheral modules. Table 27.8 Timing of On-Chip Peripheral Modules Condition A: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, Vref = 4.0 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 10 to 13.5 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Symbol Min Max Unit Test Conditions Output data delay time tPWD 100 ns Input data setup time tPRS 50 I/O ports Input data hold time tPRH 50 Figure 27.24 TPU Timer output delay time tTOCD 100 ns Timer input setup time tTICS 40 Figure 27.25 Timer clock input setup time tTCKS 40 ns Figure 27.26 Single edge tTCKWH 1.5 tcyc Timer clock pulse width Both edges tTCKWL 2.5 TMR Timer output delay time tTMOD 100 ns Figure 27.27 Timer reset input setup time tTMRS 50 ns Figure 27.29 Timer clock input setup time tTMCS 50 ns Figure 27.28 Single edge tTMCWH 1.5 Timer clock pulse width Both edges tTMCWL 2.5 tcyc WDT1 BUZZ output delay time tBUZD 100 ns Figure 27.30 SCI Asynchronous tScyc 4 tcyc Input clock cycle Synchronous 6 Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr 1.5 tcyc Input clock fall time tSCKf 1.5 Figure 27.31 Transmit data delay time tTXD 100 ns Receive data setup time (synchronous) tRXS 75 ns Receive data hold time (synchronous) tRXH 75 ns Figure 27.32 A/D converter Trigger input setup time tTRGS 40 ns Figure 27.33 |
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