H8SSLASH2225 datasheet(131/1071 Pages) RENESAS

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Section 1 Overview

Rev. 5.00 Aug 08, 2006 page 45 of 982

REJ09B0054-0500

Pin No.

Type

Symbol

TFP-100B

TFP-100BV

FP-100B

FP-100BV

FP-100A

FP-100AV

I/O

Function

Clock

OSC2

Input

Connects to a 32.768 kHz crystal

resonator. See section 23, Clock Pulse

Generator, for typical connection diagrams

for a crystal resonator.

Output

Supplies the system clock to external

devices.

Operating

mode

control

MD2

MD1

MD0

Input

Sets the operating mode. Inputs at these

pins should not be changed during

operation. Except for mode changing, be

sure to fix the levels of the mode pins

(MD2 to MD0) by pulling them down or

pulling them up until the power turns off.

System

control

RES*

Input

Reset input pin. When this pin is low, the

chip enters the power-on reset state.

MRES

Input

When this pin is low, the chip enters the

manual reset state.

STBY*

Input

When this pin is low, a transition is made

to hardware standby mode.

BREQ

Input

Used by an external bus master to request

the bus mastership to this LSI.

BACK

Output

Indicates that the bus mastership has

been granted to an external bus master.

FWE

Input

Enables/disables programming the flash

memory.

Interrupts

NMI*

Input

Nonmaskable interrupt pin. If this pin is not

used, it should be fixed high.

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

Input

These pins request a maskable interrupt.

Address

bus

A23 to

37 to 15,

40 to 18,

Output

Outputs Address.

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