H8SSLASH2225 datasheet(132/1071 Pages) RENESAS

132 / 1071 page

Section 1 Overview

Rev. 5.00 Aug 08, 2006 page 46 of 982

REJ09B0054-0500

Pin No.

Type

Symbol

TFP-100B

TFP-100BV

FP-100B

FP-100BV

FP-100A

FP-100AV

I/O

Function

Data bus

D15 to

100 to 96,

11 to 1

100, 99,

14 to 1

Input/

output

Used as the bidirectional data bus.

Bus

control

CS7

CS6

CS5

CS4

CS3

CS2

CS1

CS0

Output

Select signals for areas 7 to 0.

Output

When this pin is low, it indicates valid

address output on the address bus.

Output

When this pin is low, it indicates that the

external address space is being read.

HWR

Output

Strobe signal: Writes to the external

address bus to indicate valid data on the

upper data bus (D15 to D8).

LWR

Output

Strobe signal: Writes to the external bus to

indicate valid data on the lower data bus

(D7 to D0).

WAIT

Input

Requests insertion of wait states in bus

cycle when accesses to the external three-

state address.

16-bit timer-

pulse unit

(TPU)

TCLKD

TCLKC

TCLKB

TCLKA

Input

These pins input an external clock.

TIOCA0

TIOCB0

TIOCC0

TIOCD0

Input/

Output

Pins for the TGRA_0 to TGRD_0 input

capture input, output compare output, or

PWM output.

TIOCA1

TIOCB1

Input/

Output

Pins for the TGRA

_1 and TGRB_1 input

capture input, output compare output, or

PWM output.

TIOCA2

TIOCB2

Input/

Output

Pins for the TGRA

_2 and TGRB_2 input

capture input, output compare output, or

PWM output.

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