H8SSLASH2225 datasheet(150/1071 Pages) RENESAS

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Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 64 of 982

REJ09B0054-0500

• High-speed operation

 All frequently-used instructions execute in one or two states

 8/16/32-bit register-register add/subtract : 1 state

 8 × 8-bit register-register multiply

: 12 states

 16 ÷ 8-bit register-register divide

: 12 states

 16 × 16-bit register-register multiply

: 20 states

 32 ÷ 16-bit register-register divide

: 20 states

• Two CPU operating modes

 Normal mode*

 Advanced mode

• Power-down state

 Transition to power-down state by a SLEEP instruction

 CPU clock speed selection

Note: * Normal mode is not available in this LSI.

2.1.1

Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.

• Register configuration

 The MAC register is supported by the H8S/2600 CPU only.

• Basic instructions

 The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the

H8S/2600 CPU only.

• The number of execution states of the MULXU and MULXS instructions;

Execution States

Instruction

Mnemonic

H8S/2600

H8S/2000

MULXU

MULXU.B Rs, Rd

MULXU.W Rs, ERd

MULXS

MULXS.B Rs, Rd

MULXS.W Rs, ERd

In addition, there are differences in address space, CCR and EXR register functions, and power-

down modes, etc., depending on the model.

H8S/2225 数据表(PDF) 150 Page - Renesas Technology Corp

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