H8SSLASH2225 datasheet(152/1071 Pages) RENESAS

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Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 66 of 982

REJ09B0054-0500

2.2

CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a

maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address

space. The mode is selected by the mode pins.

2.2.1

Normal Mode

In normal mode, the exception vector table and stack have the same structure as the H8/300 CPU.

• Address Space

Linear access is provided to a maximum address space of 64 kbytes.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even

when the corresponding general register (Rn) is used as an address register. If the general

post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding

extended register (En) will be affected.

• Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid.

• Exception Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception vector table. One

branch address is stored per 16 bits. Figure 2.1 shows the structure of the exception vector

table in normal mode. For details of the exception vector table, see section 4, Exception

Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address. In normal mode the operand is a 16-bit word operand,

providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000

to H'00FF. Note that this area is also used for the exception vector table.

• Stack Structure

In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call,

and the PC, condition-code register (CCR) and extended control register (EXR) are pushed

onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed

onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: Normal mode is not available in this LSI.

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