H8SSLASH2225 datasheet(176/1071 Pages) RENESAS

176 / 1071 page

Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 90 of 982

REJ09B0054-0500

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

EA(disp)

BRA d:16, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

(4) Operation field, effective address extension, and condition field

Figure 2.11 Instruction Formats (Examples)

2.7

Addressing Modes and Effective Address Calculation

The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses

a subset of these addressing modes. Arithmetic and logic instructions can use the register direct

and immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit manipulation instructions use register direct, register

indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR,

BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in

the operand.

Table 2.11 Addressing Modes

No.

Addressing Mode

Symbol

@ERn

@(d:16,ERn)/@(d:32,ERn)

@ERn+

@–ERn

Absolute address

@aa:8/@aa:16/@aa:24/@aa:32

Immediate

#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Memory indirect

@@aa:8

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