H8SSLASH2225 datasheet(253/1071 Pages) RENESAS

253 / 1071 page

Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 167 of 982

REJ09B0054-0500

7.2

Input/Output Pins

Table 7.1 summarizes the pins of the bus controller.

Table 7.1

Pin Configuration

Name

Symbol

I/O

Function

Address strove

Output Strobe signal indicating that address output on

address bus is enabled.

Read

Output Strobe signal indicating that external space is being

read.

High write

HWR

Output Strobe signal indicating that external space is to be

written, and upper half (D15 to D8) of data bus is

enabled.

Low write

LWR

Output Strobe signal indicating that external space is to be

written, and lower half (D7 to D0) of data bus is

enabled.

Chip select 7 to 0

CS7 to CS0

Output Strobe signal indicating that areas 7 to 0 are selected.

Wait

WAIT

Input

Wait request signal when accessing external 3-state

access space.

Bus request

BREQ

Input

Request signal that releases bus to external device.

Bus request

acknowledge

BACK

Output Acknowledge signal indicating that bus has been

released.

7.3

The following shows the registers of the bus controller.

• Bus width control register (ABWCR)

• Access state control register (ASTCR)

• Wait control register H (WCRH)

• Wait control register L (WCRL)

• Bus control register H (BCRH)

• Bus control register L (BCRL )

• Pin function control register (PFCR)

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