H8SSLASH2225 datasheet(249/1071 Pages) RENESAS

249 / 1071 page

Section 6 PC Break Controller (PBC)

Rev. 5.00 Aug 08, 2006 page 163 of 982

REJ09B0054-0500

Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the

instruction will be one state later than in normal operation.

6.4

Usage Notes

6.4.1

Module Stop Mode Setting

PBC operation can be disabled or enabled using the module stop control register. The initial

setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode.

For details, refer to section 24, Power-Down Modes.

6.4.2

PC Break Interrupts

The PC break interrupt is shared by channels A and B. The channel from which the request was

issued must be determined by the interrupt handler.

6.4.3

CMFA and CMFB

The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or

CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt

will be requested after interrupt handling ends.

6.4.4

PC Break Interrupt when DTC and DMAC* Is Bus Master

A PC break interrupt generated when the DTC and DMAC* is the bus master is accepted after the

bus has been transferred to the CPU by the bus controller.

Note: * Supported only by the H8S/2239 Group.

6.4.5

PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA,

RTE, and RTS Instruction

Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS

instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the

instruction fetch at the next address.

H8S/2225 数据表(PDF) 249 Page - Renesas Technology Corp